Adding stdint.h, utilizing uint8_t, uint16_t, and uint32_t explicitly

[wilderfield]

The reason for this, is that a 64 bit target architecture will interpret an "int" as 64 bits, and this code would generate PCIe transactions formatted as 64 bit requests. Some endpoint designs cannot handle a 64 bit request. Perhaps in the future this code can be enhanced to support length = 64, 32, 16, or 8. Currently it supports only three sizes.

[wilderfield]

Hey Bill,

Not sure if this email will make it through...

Had to use your utility again :-)

This time.. my OS was not writing the PCI Command register during enumeration to enable mem writes...

I was always reading FFFF, and I was confused...

I was thinking maybe it would be nice to add this bit of detail to your README on pcimem.c

Just for noobs...

To enable access to BAR0, I had to use the linux utility setpci

setpci -d 10ee:7011 COMMAND=7

I am setting bus master enable, enabling mem space commands, and io space commands...

After this, my hardware began working!

I didn't hit this issue last time I was using your utility...

It must be a difference in OS policies...

In either case, my endpoint is a Xilinx PCIe Core... Vendor ID = 10EE

On Thu, Jan 21, 2016 at 6:53 AM, Bill Farrow notifications@github.com wrote:

Merged #2 https://github.com/billfarrow/pcimem/pull/2.

— Reply to this email directly or view it on GitHub https://github.com/billfarrow/pcimem/pull/2#event-521760476.

[billfarrow]

I have not run into that issue myself. I would be happy to add it to the README. Would you like to send me a Pull Request or shall I try to write something myself ?

[wilderfield]

Bill,

I have hit this a few times in my career, but at the moment I'm confused in understanding if this is the standard...

Basically if bit 1 of this register is not set, the endpoint will not process memRd or memWr TLPs.

http://wiki.xomb.org/index.php?title=PCI_Command_Register

In Xilinx PCIe endpoints these bits are zero initially, and can be written by System Software by means of a config write to offset 0x4, so it becomes a requirement that either the device driver or bios must set the bit during enumeration.

I'm not sure if this is per spec.

Anyways in my most recent experiment my system was not setting the bit, and pcimem.c was returning all FFFF*

After using setpci everything was golden...

Sent from my iPhone

On May 1, 2017, at 7:02 PM, Bill Farrow notifications@github.com wrote:

I have not run into that issue myself. I would be happy to add it to the README. Would you like to send me a Pull Request or shall I try to write something myself ?

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub, or mute the thread.