I'm working on another project right now, but if I finish in time I will take a look at this.
Thoughts:
You have two cores each with 96kB of ram. We could try creative things to transfer the data from the fifo directly into memory using dma. I don't know if there are gains from trying to grab half with each core.
We could, more likely get the data from the fifo with chip one a n ship it to the spirit. While core one is done with the fifo, let core two start the same process, interleaving the frame grabs.
Or, perhaps 1 grabs a frame uses dma to hand it off to 2. Letting one core grab frames and the other write to the display.
I just guessing, I'm not sure where any bottlenecks exist. I just see an idle core and we know the much slower atmega328 can do this at about 2- 2.5 FPS w/o fifo. The data transfer rates are really the limiters. If the data rates permit, we can actually hold 2 frames in Memphis, one in each core.
I'm working on another project right now, but if I finish in time I will take a look at this.
Thoughts:
You have two cores each with 96kB of ram. We could try creative things to transfer the data from the fifo directly into memory using dma. I don't know if there are gains from trying to grab half with each core.
We could, more likely get the data from the fifo with chip one a n ship it to the spirit. While core one is done with the fifo, let core two start the same process, interleaving the frame grabs.
Or, perhaps 1 grabs a frame uses dma to hand it off to 2. Letting one core grab frames and the other write to the display.
I just guessing, I'm not sure where any bottlenecks exist. I just see an idle core and we know the much slower atmega328 can do this at about 2- 2.5 FPS w/o fifo. The data transfer rates are really the limiters. If the data rates permit, we can actually hold 2 frames in Memphis, one in each core.
Sorry for the probably off base rambling.
Very Cool Project!!!