Get Ethernet core up and running

[martijnbastiaan]

To be used to extract data for Callisto clock control experimentation platform

[martijnbastiaan]

Updates:

• Core runs, but loopback mode drops packets.

[martijnbastiaan]

Updates:

• Multiple FPGA discovery working
• @martijnbastiaan thinks we should run a soft core and use lwip.

[martijnbastiaan]

Updates:

• UDP "works": 3% packet loss
• Can convert AXI (ethernet core) to Wishbone (our CPU)
• LWIP: uses Ethernet Lite core (max 100 mbit/s) - uses Microblaze/Vitis. Loads of problems, hard to debug because of the Vivado/Vitis stack.
• Next steps:
  • Debugging MDIO interface - seems to be stuck on auto-negotation.
  • Plan B: strip UDP core to to bare minimum
  • Plan C: can we do reliable UDP?

[martijnbastiaan]

Updates:

• Stripped UDP core down to bare minimum
• Ethernet FIFO working
• Still need to write C driver
• Leon remarks that we probably need some clock/timer for TCP stack

[martijnbastiaan]

Updates:

• Can instantiate a soft-core with boot program
• Making transmit-buffer for Ethernet packages