Add software test set up and tear down

[martijnbastiaan]

After merging https://github.com/bittide/bittide-hardware/pull/424 we're stuck with a pretty TODO in our code base:

    -- TODO: We used to perform a HITL test where the CPU would write to a success
    --       register (or a failure register when it would get trapped). We
    --       currently load programs over JTAG instead of preloading them in the
    --       bitstream, making this impossible to do. We should add a _pre_
    --       processing step to the HITL infrastructure, restoring the ability to
    --       do this once more.

This is probably a matter of adding a "set up" and "tear down" stage after each test. I'm not sure how we're going to manage this in TCL, it seems pretty dreadful to program it there..

This structure should be able to be used for:

• Loading programs over JTAG
• Monitoring interfaces such as UART and Ethernet
• Collecting and processing data

[martijnbastiaan]

After thinking about it a little bit, my proposal would be to write a small wrapper around Vivado that allows us to control it from Haskell - similar to what doctest-parallel does with ghci. As a bonus, it would make it trivial to do parallel FPGA programming, VIO monitoring, etc.

[martijnbastiaan]

After https://github.com/bittide/bittide-hardware/pull/536 we can control Vivado from Haskell, resolving the biggest part of this issue. Last part is added in https://github.com/bittide/bittide-hardware/pull/664.