CtxLink_usb

[sidprice]

Detailed description

This is an initial PR to bring ctxLink with basic USB functionality into the upstream repository.

TRACESWO is not tested/implemented in this firmware. It will be added in the future when the ongoing F4 TRACESWO work is merged into main.

Your checklist for this pull request

• [x] I've read the Code of Conduct
• [x] I've read the guidelines for contributing to this repository
• [x] It builds for hardware native (see Building the firmware)
• [x] It builds as BMDA (see Building the BMDA)
• [x] I've tested it to the best of my ability
• [x] My commit messages provide a useful short description of what the commits do

[ALTracer]

To facilitate bringup of TraceSWO Async support via in-tree drivers, please document relevant chip resources in platform.h. I understand that it'll be PC7, USART6_RX, DMA2 Channel 5 Stream 1/2, and some SRAM. Possibly TIM3_CH2 (for Manchester) on same pin. Is JTDO_PIN PC6 or PC7 on all PCB revisions (green LED1 idle/run)? Otherwise one could use HDSEL as single-wire half-duplex receiver from USART6_TX pin but it's a hack -- full pinswap is only available in newer IP versions. I expect this F401RE to behave in a similar way to F411CE, that is 84MHz APB2 and OVER8 gives 10.5 Mbaud; OVER16 supported by libopencm3 gives 5.25 Mbaud, or with a BRR of 21 an even 4Mbaud. If you tested practical limits with your out-of-tree fork, it would be nice to have them recorded here in the platform header or README.md.

[sidprice]

@ALTracer Thanks for the comments, once we have the basic USB PR handled I will revisit your comments, Sid