blackmesalabs / sump2

open-source logic analyzer for FPGAs
GNU General Public License v3.0
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sump2.py crashes on a very simple VCD file generated by iverilog #6

Open afiskon opened 6 years ago

afiskon commented 6 years ago

File example: https://afiskon.ru/s/20/502005b771_hello.vcd.txt

sump2.py crashes with following errors:

vcdfile2signal_list() : Parsing VCD Symbol Definitions
top_module is  hello_sim
1000
vcdfile2signal_list() : Parsing VCD Value Change Dumps
0%
5%
10%
15%
20%
25%
30%
35%
40%
44%
49%
54%
60%
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90%
95%
vcdfile2signal_list() : Complete : Time 0.005s : Rate 0.0112 MSPS
Traceback (most recent call last):
  File "./sump2.py", line 7223, in <module>
    main = main();
  File "./sump2.py", line 692, in __init__
    proc_cmd( self, words[0],words[1:] );
  File "./sump2.py", line 1993, in proc_cmd
    rts = load_vcd( self, parms );
  File "./sump2.py", line 1888, in load_vcd
    proc_cmd( self, "zoom_to", ["0", str( self.max_samples ) ] );# Redraws
  File "./sump2.py", line 3212, in proc_cmd
    screen_refresh( self );
  File "./sump2.py", line 3613, in screen_refresh
    draw_screen( self ); # Draw the new stuff
  File "./sump2.py", line 4060, in draw_screen
    sig_obj.format,format_bin, x,y);
  File "./sump2.py", line 4455, in draw_sample
    txt_width = len( val ) * self.txt_width;
TypeError: object of type 'bool' has no len()

GTK Wave (v 3.3.86) has no problems with this file:

https://afiskon.ru/s/c5/f4c2825bc9_temp.png

afiskon commented 6 years ago

Here is how I got this particular file.

Project: https://github.com/afiskon/icestick-first-project/tree/master/sim

iverilog -g2012 -o sim hello.sv hello_sim.sv
./sim
blackmesalabs commented 6 years ago

sump2.py doesn't like the whitespace "b1 !" between the binary values and the net symbol. This seemed to work fine "b1!". I will look into this. Thanx.