What is pluggable pipeline?

[Honourable-A]

Hi, I tried to understand the concept behind pluggable pipeline but could not till now. Usually, instruction set architecture or the group of instructions for a architecture are defined by the set of instructions that can be decoded by the decoder in the pipeline. But here the pipeline is different from the instruction set. What is the meaning of this and how pipelines are running code without first decoding them? There is also one SIMT pipeline apart from normal or simple pipeline. Are they going to run in parallel or only one of them will work at a time because they are pluggable? These questions may not sound good because many of them resulted of my guesing. But if you can answer or point me to some document that will be helpful.

[mn416]

It simply means that the pipeline and instruction set have been defined mostly independently of each other, improving modularity. For example, I can define the RV32I instruction set once. Then I connect it to a 5-stage pipeline to make a CPU core, or a SIMT pipeline to make a GPGPU, or a maybe even an OoO pipeline to make a superscalar CPU core. So from a single implementation of the instruction set, I could make three different kinds of processor. It is the instruction set definition (i.e source code) that is being shared, not the hardware that implements it.

[Honourable-A]

Thank you very much for your explanation. I have another doubt as I mentioned in my earlier question. The SIMT and simple pipeline are both available in this pebbles project. How will one be selected during execution? Or only one will be enabled in one design and it is up to the designer to enable one pipeline? Or one will be selected based on some other method from the code? Actually, SIMTight SoC uses this structure and there also SIMT and simple pipeline are present but there the simple core is the host core which uses SIMT core as a coprocessor which is probably different from the pluggable pipeline concept in this project. But I am confused how this pebbles SIMT and simple core are used in SIMTight SoC. If you kindly give some insight that will be very helpful.

[mn416]

There is no choice between pipelines "during execution". The choice of which pipeline to use is made when you implement your core. The choice is yours, as the developer. This concept is indeed used in the SIMTight SoC to implement the CPU core and the SIMT core. Both of these cores use the same definition of the RV32IMAxCHERI instruction set, but different pipelines. As I said before, this does not mean the two cores share hardware. They share "modules" in the modular programming sense, e.g. two different programs using the same library for linked lists do not share the same linked list.