Closed rakita closed 3 months ago
Current revm 11.0 is conflicting with alloy-eips 0.1.5 (which includes https://github.com/alloy-rs/alloy/commit/5d8dce4b542a069d0aa2973e7705309422311de6) because of lacking this PR.
Compiling revm-primitives v6.0.0
error[E0107]: struct takes 0 generic arguments but 1 generic argument was supplied
--> /home/mio/.cargo/registry/src/index.crates.io-6f17d22bba15001f/revm-primitives-6.0.0/src/env/eip7702.rs:9:16
|
9 | Signed(Vec<SignedAuthorization<Signature>>),
| ^^^^^^^^^^^^^^^^^^^----------- help: remove these generics
| |
| expected 0 generic arguments
|
note: struct defined here, with 0 generic parameters
--> /home/mio/.cargo/registry/src/index.crates.io-6f17d22bba15001f/alloy-eips-0.1.5/src/eip7702/auth_list.rs:75:12
|
75 | pub struct SignedAuthorization {
| ^^^^^^^^^^^^^^^^^^^
yanked the releases, should be done as minor, not patch
Valgrind Results:
==4076== Cachegrind, a cache and branch-prediction profiler
==4076== Copyright (C) 2002-2017, and GNU GPL'd, by Nicholas Nethercote et al.
==4076== Using Valgrind-3.18.1 and LibVEX; rerun with -h for copyright info
==4076== Command: target/release/snailtracer
==4076==
--4076-- warning: L3 cache found, using its data for the LL simulation.
Running snailtracer example!
elapsed: 1.841954298s
==4076==
==4076== I refs: 427,040,162
==4076== I1 misses: 3,322
==4076== LLi misses: 2,849
==4076== I1 miss rate: 0.00%
==4076== LLi miss rate: 0.00%
==4076==
==4076== D refs: 204,076,940 (132,268,735 rd + 71,808,205 wr)
==4076== D1 misses: 339,968 ( 199,994 rd + 139,974 wr)
==4076== LLd misses: 137,816 ( 4,496 rd + 133,320 wr)
==4076== D1 miss rate: 0.2% ( 0.2% + 0.2% )
==4076== LLd miss rate: 0.1% ( 0.0% + 0.2% )
==4076==
==4076== LL refs: 343,290 ( 203,316 rd + 139,974 wr)
==4076== LL misses: 140,665 ( 7,345 rd + 133,320 wr)
==4076== LL miss rate: 0.0% ( 0.0% + 0.2% )
Will merge it with alloy patches and we can make additional PR that uses crates version
Few things added, still WIP:
authorization.address
and not fromauthority