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bluespec / AWSteria_Infra

"Middleware" (infrastructure) for host-FPGA applications (e.g., accelerators)
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TestApp, Verilator build, Missing mkAWSteria_System.v #5

Closed jahagirdar closed 2 years ago

jahagirdar commented 2 years ago

Running make all in AWSteria_Infra/TestApp/HW/build_Verilator results in the following error.

INFO: Editing Verilog_RTL/mkAWSteria_System.v -> Verilator_RTL/mkAWSteria_System.v for DPI-C
sed  -f /prj/tools/AWSteria_Infra/Platform_Sim/HW/Verilator_resources/sed_script.txt  Verilog_RTL/mkAWSteria_System.v  > Verilator_RTL/mkAWSteria_System.v
sed: can't read Verilog_RTL/mkAWSteria_System.v: No such file or directory
make: *** [/prj/tools/AWSteria_Infra/Platform_Sim/HW/Include_Verilator.mk:78: simulator] Error 2
rsnikhil commented 2 years ago

Fixed (temporary; cleaner fix will follow later).

The Verilator Makefile expects a mkAWSteria_System module (based on a different app than TestApp) so that it can manipulate, with sed, the calls for imported C functions. The cleaner fix: recently bsc has been upgraded to include Verilator as a standard simulator; the Makefile needs to be fixed up for that.

rsnikhil commented 2 years ago

Closed