Closed Verdvana closed 4 years ago
Dear Verdvana,
I used Google Translate to understand your comment:
"There is no mkBRVF_Core.v file at all"
There has not been any 'BRVF_Core.bsv', nor Verilog 'mkBRVF_Core.v' for a long time now (more than a year?). Things have evolved quite a bit since then.
Please see: Doc/Microarchitecture/Microarchitecture.pdf for some notes on the module hierarchy.
Briefly, the module hierarchy looks like this:
mkTop_HW_Side
mkSoC_Top
mkCore
mkCPU
mkSoC_Map
mkFabric_2x3
mkNear_Mem_IO_AXI4
mkPLIC_16_2_7
mkDebug_Module
mkTV_Encode
mkSoC_Map
mkFabric_AXI4
mkBoot_ROM
mkMem_Controlloer
mkAX4_Deburster_A (2x)
mkUART
mkMem_Model
Roughly speaking, the old BRVF_Core.bsv => src_Core/Core/Core.bsv and mkBRVF_Core.v => mkCore.v
Dear Rishiyur S. Nikhil:
Thanks Reply!
After reading your instructions, I understand now, thank you!
從我的iPhone傳送
Rishiyur S. Nikhil notifications@github.com 於 2020年4月8日 下午9:42 寫道:
Dear Verdvana,
I used Google Translate to understand your comment:
"There is no mkBRVF_Core.v file at all"
There has not been any 'BRVF_Core.bsv', nor Verilog 'mkBRVF_Core.v' for a long time now (more than a year?). Things have evolved quite a bit since then.
Please see: Doc/Microarchitecture/Microarchitecture.pdf for some notes on the module hierarchy.
Briefly, the module hierarchy looks like this:
mkTop_HW_Side mkSoC_Top mkCore mkCPU mkSoC_Map mkFabric_2x3 mkNear_Mem_IO_AXI4 mkPLIC_16_2_7 mkDebug_Module mkTV_Encode mkSoC_Map mkFabric_AXI4 mkBoot_ROM mkMem_Controlloer mkAX4_Deburster_A (2x) mkUART mkMem_Model
Roughly speaking, the old BRVF_Core.bsv => src_Core/Core/Core.bsv and mkBRVF_Core.v => mkCore.v
— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub, or unsubscribe.
I finally understood the source of the confusion. 'mkBRVFCore' was mentioned in the README file which you must have read. I have now updated the README file. My apologies for the confusion.
压根也没有mkBRVF_Core.v这个文件