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bluespec / Piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
Apache License 2.0
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verbosity of MMU_Cache is always 0 #12

Closed TarekIbnZiad closed 4 years ago

TarekIbnZiad commented 5 years ago

When you set the verbosity of the CPU to be 1 or 2, the verbosity of the MMU_Cache.bsv file is stuck-at-0. Hence, none of the display messages of this file can be displayed during simulation. This can be verified by running any isa test with VERBOSITY=+v1 or VERBOSITY=+v2 and checking the output log.

I believe the problem is that although MMU_Cache.bsv has a set_verbosity method, there is no way to reach it as the Near_Mem_IFC.bsv file doesn't have one.

One possible solution is to add set_verbosity method to the Near_Mem_IFC.bsv file (with a proper body in Near_Mem_Caches.bsv) and call it in the set_verbosity method of the CPU.bsv file. https://github.com/bluespec/Piccolo/blob/master/src_Core/Core/CPU.bsv#L1477-L1480

Thank you

rsnikhil commented 4 years ago

Yes, you are correct, but I'm leaving it as it is.

One typically wants to selectively fix verbosity on one of many possible modules, briefly while debugging it, and rather than designing some dynamic mechanism for such fine-grain (per module) control of verbosity, I find it's easy enough just to temporarily edit the verbosity declaration in the module of interest and recompile it, and restore it when done.