Add constraints to Xilinx IP project for preserving the JTAG Clock. Also add clock uncertainty to ensure hold times are met.
This involved creating a new src/p1_constraints.xdc file with the relevant commands and modifying the component.xml file to the new file. The mark debug constraint is used during out-of-context synthesis to preserve the internally generated JTAG clock signal. The create clock and clock uncertainty commands are then generalized by vivado during the final synth/impl steps to ensure the data path is constrained and hold times are met.
Add constraints to Xilinx IP project for preserving the JTAG Clock. Also add clock uncertainty to ensure hold times are met.
This involved creating a new src/p1_constraints.xdc file with the relevant commands and modifying the component.xml file to the new file. The mark debug constraint is used during out-of-context synthesis to preserve the internally generated JTAG clock signal. The create clock and clock uncertainty commands are then generalized by vivado during the final synth/impl steps to ensure the data path is constrained and hold times are met.