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bluespec / Piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
Apache License 2.0
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SC to 4-byte aligned but not 8-byte aligned address will always report success #18

Closed PeterRugg closed 4 years ago

PeterRugg commented 4 years ago

Since the MMU Cache shifts the memory access result based on the alignment of the address request, and the 1 to indicate SC failure is passed through the same logic, the 1 is shifted out in the case that the address is misaligned, leaving 0 which falsely indicates success.

Example code sequence: auipc a0, 0x0 addi a0,a0,52 # load 4-byte but not 8-byte aligned value into a0 li a1, 42 # arbitrary value to be stored sc.w a2, a1,(a0) # perform an SC that should fail (no paired LL)

Piccolo RV32ACIMU currently returns 0 in this case.

jrtc27 commented 4 years ago

Assembly snippet that doesn't hard-code the address:

entry:
    lla a0, bar
    li a1, 42
    sc.w a2, a1, (a0)

    .balign 8
    .4byte 0
    # Now only 4-byte aligned
bar:
    .4byte 0
rsnikhil commented 4 years ago

Fixed in MMU_Cache.bsv in both Piccolo and Flute