Make SRET illegal when S-mode not supported

bluespec / Piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

Apache License 2.0

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Closed PeterRugg closed 4 years ago

PeterRugg commented 4 years ago

The RISC-V spec says this should be the behaviour.

Also applies to Flute.