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bluespec / Piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)
Apache License 2.0
311 stars 49 forks source link

AXI Fabric bugs #30

Open ZipCPU opened 4 years ago

ZipCPU commented 4 years ago

I recently took an opportunity to review mkFabric_AXI4.v using a formal AXI4 property checker under SymbiYosys. It appears to have some difficulties routing packets from the correct source to the correct destination. The attached (abbreviated) trace should give you an idea of what I'm talking about.

bad-wstrb

In this example, a burst packet presented from master 0 gets routed to slave 0. The associated W* channel data, however, gets corrupted in the process. (The appropriate WSTRB value sent by the master was 0, not 4.) Not shown are two similar bursts presented from master 1 during this time which may (or may not be) relevant.

Dan

rsnikhil commented 4 years ago

Hello, Dan, just acknowledging your report to assure you it hasn't fallen through the cracks; I will study it as soon as I can (currently swamped on another project). Rgds.