Building and Running from the Verilog Sources, out of the box results in Error

bluespec / Piccolo

RISC-V CPU, simple 3-stage pipeline, for low-end applications (e.g., embedded, IoT)

Apache License 2.0

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Closed nishanthsmurthy24 closed 3 years ago

nishanthsmurthy24 commented 3 years ago

Execution of $make simulator

in the builds/<ARCH>_<CPU>_verilator/

directory results in %Warning-DEPRECATED: Verilog_RTL/mkTop_HW_Side_edited.v:7: Deprecated -msg in configuration files, use -rule instead.

%Error: Exiting due to 6 warning(s) make: *** [../../builds/Resources/Include_verilator.mk:52: simulator] Error 1

How to resolve this error?

quark17 commented 3 years ago

This was fixed in commit 874ab85d by updating the lint_off statements in the Verilator config file.