This set of changes prevents speculation in 3 places to reduce DRAM traffic (~13% across our MiBench benchmarks).
The first is to prevent instructions that jump to a register target and do not have a prediction from the BTB from speculating the default prediction (straight through). Instead, we flush the fetch pipeline and wait for redirection.
The second and third are by not performing a page table walk for invalid virtual addresses in the instruction and data TLBs. Previously, even if the upper bits of a pointer did not constitute a valid virtual address, the would-be virtual page number was still fed into the page walker and a page table walk was done on them. We now check that the upper bits are a valid sign extension, and fail early if not, preventing a table walk.
This set of changes prevents speculation in 3 places to reduce DRAM traffic (~13% across our MiBench benchmarks). The first is to prevent instructions that jump to a register target and do not have a prediction from the BTB from speculating the default prediction (straight through). Instead, we flush the fetch pipeline and wait for redirection. The second and third are by not performing a page table walk for invalid virtual addresses in the instruction and data TLBs. Previously, even if the upper bits of a pointer did not constitute a valid virtual address, the would-be virtual page number was still fed into the page walker and a page table walk was done on them. We now check that the upper bits are a valid sign extension, and fail early if not, preventing a table walk.