bmpenuelas / systemverilog-formatter-vscode

Beautify SystemVerilog code in VSCode through Verible
MIT License
17 stars 4 forks source link

Can Windows 10 systems customize formatting styles themselves? #21

Closed VectorNO1 closed 3 months ago

VectorNO1 commented 10 months ago

By default, the formatting of various code snippets is automatically inferred from existing code, which is not in line with my usage habits. I hope that all port declarations, assignments, etc. in the code can be aligned.

bmpenuelas commented 10 months ago

Hi, to configure the usage of verible you have to refer to the verible formatter arguments: https://github.com/chipsalliance/verible/tree/master/verilog/tools/formatter

Your chosen arguments shall then be added in the VSCode config as described here: https://github.com/bmpenuelas/systemverilog-formatter-vscode#configuration