Standardise communication method with Vidor FPGA through the Ardunio Vidor USB connection.
Implement PCIe communication (included with the board) to a host machine
Implement some DSP algorithm suite in HDL. Ideally use both an IP block and own implementation of common algorithm. FFT is tempting.
Bonus: Implement wifi connection and basic server (may be best accomplished with a combination of the onboard MCU and FPGA) to apply DSP algorithms as a service.
Core issue for project.
Core specifications:
Challenging! Longer-term project.