Closed btashton closed 3 years ago
The reset functions in the ROM have a bug where they do not first clear the swrst bit prior to writing it. This means that if you issue a GLB_SW_System_Reset twice the second one will hang in the while loop.
GLB_SW_System_Reset
ROM function looks like this
void GLB_SW_System_Reset(void) { _BL602_HBN_GLB = _BL602_HBN_GLB & 0xfffffffc; _BL602_CLK_CFG0 = _BL602_CLK_CFG0 & 0xff0000ff; _DAT_40000ffc = 0; _BL602_SWRST_CFG2 = _BL602_SWRST_CFG2 & 0xfffffff8 | 6; do { BL602_Delay_US(10); } while( true ); }
should be
void GLB_SW_System_Reset(void) { _BL602_HBN_GLB = _BL602_HBN_GLB & 0xfffffffc; _BL602_CLK_CFG0 = _BL602_CLK_CFG0 & 0xff0000ff; _DAT_40000ffc = 0; _BL602_SWRST_CFG2 = _BL602_SWRST_CFG2 & 0xfffffff8; _BL602_SWRST_CFG2 = _BL602_SWRST_CFG2 & 0xfffffff8 | 6; do { BL602_Delay_US(10); } while( true ); }
Can we also get some documentation on what register at address 0x40000ffc does? It seems to be reset when the root clock is updated
0x40000ffc
I was wrong. This function does clear the bit before setting it.
The reset functions in the ROM have a bug where they do not first clear the swrst bit prior to writing it. This means that if you issue a
GLB_SW_System_Reset
twice the second one will hang in the while loop.ROM function looks like this
should be
Can we also get some documentation on what register at address
0x40000ffc
does? It seems to be reset when the root clock is updated