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bperez77 / xilinx_axidma

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
MIT License
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Resetting the DMA IP and drivers #106

Open formidable01 opened 4 years ago

formidable01 commented 4 years ago

We often get into a situation in which the DMA errors out. Specifically, the TX does not complete (it is run using oneway transfers with no wait). The receive side then times out because no data arrives. When we shut down the receive and try to restart the DMA operations neither side works unless we unload and reload the dma drivers.

There has to be a better way to reset the drivers and the DMA IP but I am not sure I know what it is. If you have any ideas or guidance that would be great.

formidable01 commented 4 years ago

I received the following perhaps relevant response on the Xilinx message boards https://forums.xilinx.com/t5/Serial-Transceivers/XAPP-1198-targetting-UltraScale-XCVU095-FFVB2104E/m-p/1008258#M5068 broadly stating that AXI doesn't tolerate incomplete transactions and that in order to reset a situation born of an incomplete transaction additional IP needs to be employed

SmartElec commented 3 years ago

Same with you