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bperez77 / xilinx_axidma

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
MIT License
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When to start oneway transfer in PS? #135

Open BaronMunchhausen opened 3 years ago

BaronMunchhausen commented 3 years ago

Hi,

I am setting up a system, which uses a Custom IP to read data from an ADC and transfer it with AXI DMA to the PS. I am wondering, how the PS can know when to start the axidma_oneway_transfer to get the data. The PS does start the ADC sampling, but does not exactly know when the custom IP transfers the data. Can I just start the oneway transfer in blocking mode after starting the ADC and the transfer starts as soon as the transfer finishes? Or might I get some data before the DMA transfer has finished?

Am I right, that the callback function this driver provides, fires after axidma_oneway_transfer has finished and is therefore not suitable for my problem? Is it possible to use s2mm_introut interrupt of AXI DMA IP with this driver?

I am not sure if got the interaction between the driver and the AXI DMA IP right and would be thankful for any advice.

samberhanu commented 2 years ago

you're better off using the central DMA IP and driver (directly from Xilinx) unless you can FIFO your data and fire-off your PS code right away. The driver will fail if there's no FIFO data available and so you can retry it on that.

On another note, I had some serious issues with this driver and had to accomodate the troubles by writing extra HDL code as no one bothered to respond. It's a great driver but there are some details that you find out on your own upon trying to use the driver. Good luck