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bperez77 / xilinx_axidma

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
MIT License
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DMA receive transaction timed out #43

Closed sk2046 closed 6 years ago

sk2046 commented 6 years ago

Hi bperez77,

I am trying to install your driver for using with DMA on petalinux 2017.4 and run into some problems. Here is what I have done:

root@zynq_petalinux:/lib/modules/4.9.0-xilinx-v2017.4/extra# insmod ./xilinx-axidma.ko 
xilinx_axidma: loading out-of-tree module taints kernel.
axidma: axidma_dma.c: axidma_dma_init: 706: DMA: Found 1 transmit channels and 1 receive channels.
axidma: axidma_dma.c: axidma_dma_init: 708: VDMA: Found 0 transmit channels and 0 receive channels.

It is OK.

root@zynq_petalinux:/usr/bin# ./axidma_benchmark -i 1 -o 1
AXI DMA Benchmark Parameters:
        Transmit Buffer Size: 1.00 Mb
        Receive Buffer Size: 1.00 Mb
        Number of DMA Transfers: 1000 transfers

Using transmit channel 0 and receive channel 1.
axidma: axidma_dma.c: axidma_start_transfer: 298: DMA receive transaction timed out.`

What's the problem?Thank you.

sk2046 commented 6 years ago

Sometimes the error like this: https://forums.xilinx.com/t5/Embedded-Linux/ZYNQ-7010-AXI-DMA-driver-Fail-TIMEOUT/td-p/833457

sk2046 commented 6 years ago

When i use DMA with SG mode,the problem has been solved.

bperez77 commented 6 years ago

Interesting, I'm going to have to make a note of this. The driver should work regardless of whether or not it's in SG mode. Something may have changed in the Xilinx driver. I'm going to close this issue since it's resolved.