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bperez77 / xilinx_axidma

A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
MIT License
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xilinx-vdma 40400000.dma: Channel ef27b810 has errors 10, cdr 0 tdr 0 #75

Open zhangzilin opened 5 years ago

zhangzilin commented 5 years ago

Hi Brandon,

I send data from PL to the PS side by "axidma_oneway_transfer()", then the PS side wait for an interrupt generate by fifo core in PL side, which indicate the data is ready to send to the PS.

Once the PS side capture the interrupt signal, it will use "axidma_oneway_transfer()" to read the data from PL, but there was an error: "xilinx-vdma 40400000.dma: Channel ef27b810 has errors 10, cdr 0 tdr 0".

My fifo IP is set up like this: a set of data is generated by a mechanism and stored in the FIFO. When the data is full, an interrupt signal is output to the PS.

Do you have any idea why this error appear? What method should I use to solve this problem?

Thanks very much fo your great project.

zhangzilin commented 5 years ago

I have sent the entire project to your mailbox, I hope you can take the time to view it.

My email address is 15754301550@163.com.

Thank you very much.

zhangzilin commented 5 years ago

Sorry, my email was not sent successfully.

I just found out that my FIFO IP TLAST is not connected to the DMA TLAST. Is this the error?

Thank you very much for viewing.

chris0306 commented 5 years ago

Hi Brandon,

I send data from PL to the PS side by "axidma_oneway_transfer()", then the PS side wait for an interrupt generate by fifo core in PL side, which indicate the data is ready to send to the PS.

Once the PS side capture the interrupt signal, it will use "axidma_oneway_transfer()" to read the data from PL, but there was an error: "xilinx-vdma 40400000.dma: Channel ef27b810 has errors 10, cdr 0 tdr 0".

My fifo IP is set up like this: a set of data is generated by a mechanism and stored in the FIFO. When the data is full, an interrupt signal is output to the PS.

Do you have any idea why this error appear? What method should I use to solve this problem?

Thanks very much fo your great project.

hello，zhangzilin！ I met the same vdma print，how did you resolve it？ Thanks a lot!

13ee1010 commented 2 years ago

Hello I also met with the same error. Do you know how one can solve this?

wcx11121 commented 1 year ago

me too

dantepayne commented 8 months ago

me too，although it does not affect the main function.