A zero-copy Linux driver and a userspace interface library for Xilinx's AXI DMA and VDMA IP blocks. These serve as bridges for communication between the processing system and FPGA programmable logic fabric, through one of the DMA ports on the Zynq processing system. Distributed under the MIT License.
I just started working with your library. First off: Thank you very much for your work, it helps me a lot. I was strolling around the Xilinx Forums before finding this and all solutions there are only half-baked or outdated.
While importing the driver and library to my Petalinux environment (2018.2) I came across a small issue: When including libaxidma.h and axidma_ioctl.h in Xilinx SDK from the SDK I generated with Petalinux the linker complains that "bool" is not defined. This can be solved by adding
#include <stdbool.h>
to libaxidma.h and axidma_ioctl.h.
Best regards and thanks again
Jannik
P.S.: If someone is interested I could upload my Petalinux meta-user folders for building the axidma module and library. Maybe this could be added to the Wiki?
Hi!
I just started working with your library. First off: Thank you very much for your work, it helps me a lot. I was strolling around the Xilinx Forums before finding this and all solutions there are only half-baked or outdated.
While importing the driver and library to my Petalinux environment (2018.2) I came across a small issue: When including libaxidma.h and axidma_ioctl.h in Xilinx SDK from the SDK I generated with Petalinux the linker complains that "bool" is not defined. This can be solved by adding
#include <stdbool.h>to libaxidma.h and axidma_ioctl.h.
Best regards and thanks again Jannik
P.S.: If someone is interested I could upload my Petalinux meta-user folders for building the axidma module and library. Maybe this could be added to the Wiki?