[CLOSED] Remove build script hack to delete verilog file after next CM merge

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Archive of issues in brackets.

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Open core-ai-bot opened 3 years ago

core-ai-bot commented 3 years ago

Issue by njx Friday Mar 01, 2013 at 18:13 GMT Originally opened as https://github.com/adobe/brackets/issues/3009

Marijn got rid of the LGPL sample code from the Verilog mode demo, so we can remove our rm hack after the next upstream merge.

core-ai-bot commented 3 years ago

Comment by pthiess Friday Mar 01, 2013 at 21:41 GMT

Assigned to you,@njx to track & trigger

core-ai-bot commented 3 years ago

Comment by njx Tuesday Mar 12, 2013 at 22:23 GMT

Upstream CM with the change has been merged, so we can remove this now. Low priority to@gruehle

core-ai-bot commented 3 years ago

Comment by gruehle Tuesday Apr 16, 2013 at 17:46 GMT

This was removed in adobe/brackets-shell#219. Closing.