Right now we model a very simplistic, single-level cache. It would be nice to make our simulated cache more realistic by exposing tweakable parameters:
Cache line size
Number of lines in cache
Direct-mapped, 2^n-way associative, or fully-associative
... others?
Perhaps also number of caches, and cost of cache miss?
Right now we model a very simplistic, single-level cache. It would be nice to make our simulated cache more realistic by exposing tweakable parameters:
Perhaps also number of caches, and cost of cache miss?