Building Sargantana with MEEP Shell

[davidcastells]

I am facing some problems building Sargantana with the MEEP Shell

I follow this process:

source /tools/Xilinx/Vivado/2023.2/settings64.sh
git clone https://github.com/bsc-loca/fpga-shell
cd fpga-shell
make initialize LOAD_EA=sargantana  
make project
make bitstream

And I get the following errors

....

ERROR: [Synth 8-91] ambiguous clock in event control [/home/dcastells/INT_Sargantana/fpga-shell/accelerator/rtl/interface_dcache/rtl/dcache_interface.sv:145]
ERROR: [Synth 8-6156] failed synthesizing module 'dcache_interface' [/home/dcastells/INT_Sargantana/fpga-shell/accelerator/rtl/interface_dcache/rtl/dcache_interface.sv:23]
ERROR: [Synth 8-6156] failed synthesizing module 'top_tile' [/home/dcastells/INT_Sargantana/fpga-shell/accelerator/rtl/top_tile.sv:21]
ERROR: [Synth 8-6156] failed synthesizing module 'axi_wrapper' [/home/dcastells/INT_Sargantana/fpga-shell/accelerator/fpga/common/rtl/axi_wrapper.sv:23]
ERROR: [Synth 8-6156] failed synthesizing module 'sargantana_wrapper' [/home/dcastells/INT_Sargantana/fpga-shell/accelerator/fpga/meep_shell/src/sargantana_wrapper.sv:23]
ERROR: [Synth 8-6156] failed synthesizing module 'system_top' [/home/dcastells/INT_Sargantana/fpga-shell/src/system_top.sv:24]
---------------------------------------------------------------------------------
Finished RTL Elaboration : Time (s): cpu = 00:00:08 ; elapsed = 00:00:08 . Memory (MB): peak = 3367.672 ; gain = 601.223 ; free physical = 27417 ; free virtual = 50073
---------------------------------------------------------------------------------
RTL Elaboration failed
INFO: [Common 17-83] Releasing license: Synthesis
294 Infos, 147 Warnings, 1 Critical Warnings and 7 Errors encountered.
synth_design failed
ERROR: [Common 17-69] Command failed: Synthesis failed - please see the console or run log file for details
INFO: [Common 17-206] Exiting Vivado at Tue May 14 19:50:07 2024...
[Tue May 14 19:50:08 2024] synth_1 finished
ERROR: [Vivado 12-13638] Failed runs(s) : 'synth_1'
wait_on_runs: Time (s): cpu = 00:46:12 ; elapsed = 00:00:31 . Memory (MB): peak = 3454.234 ; gain = 0.000 ; free physical = 30195 ; free virtual = 52851
ERROR: [Common 17-39] 'wait_on_runs' failed due to earlier errors.

    while executing
"wait_on_run synth_1"
    (procedure "synthesis" line 24)
    invoked from within
"synthesis $g_root_dir $g_number_of_jobs"
    (file "/home/dcastells/INT_Sargantana/fpga-shell/tcl/gen_synthesis.tcl" line 94)
INFO: [Common 17-206] Exiting Vivado at Tue May 14 19:50:08 2024...
make: *** [Makefile:105: /home/dcastells/INT_Sargantana/fpga-shell/dcp/synthesis.dcp] Error 1

[ArnauBigas]

Hi,

I don't think we've ever seen this message. I notice you are using Vivado 2023, which we have never used before. Is there any chance you could try with Vivado 2021? More specifically, we are using version 2021.2.

In either case, I will try investigating this internally when I have some time.

Thanks!

[davidcastells]

Correct! It works with Vivado version 2021.2,

I can confirm that it fails with Vivado 2021.1 and Vivado 2023.2

[ArnauBigas]

Glad to hear that!

Unless you specifically need to use any other version of Vivado, I think we can close this issue.