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bsc-loca / core_tile

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Synthesis with fully Open Source tools #6

Open alikates opened 1 month ago

alikates commented 1 month ago

Just FYI, there's an ongoing effort to develop a SystemVerilog frontend for Yosys, and one of the goals is to be able to synthesize the whole core_tile: https://github.com/povik/yosys-slang/issues/31

ArnauBigas commented 3 weeks ago

Thanks for the heads-up!

Please, keep in mind that internally we have some "fixes" of the code in terms of linting/correctness that might make it easier for yosys to parse. I am unsure when these will be pushed.