//Kishin Douji Zenki - Tenchi Meidou requires bus hold delays on CPU I/O reads.
//smp_mem_access_times requires no bus hold delays on APU RAM reads.
if((address & 0xfffc) == 0x00f4) { //0x00f4 - 0x00f7
wait(address, 1);
uint8 data = readRAM(address);
if((address & 0xfff0) == 0x00f0) data = readIO(address);
wait(address, 1);
return data;
} else {
wait(address, 0);
uint8 data = readRAM(address);
if((address & 0xfff0) == 0x00f0) data = readIO(address);
return data;
}
The second argument to wait is "half cycles", eg only take 12 clocks instead of 24 clocks (exact amount is based on the TEST >register settings, but in 100% of cases, it's always 12/24.)
So what's actually happening here is that SMP reads from internal functionality (eg timers and RAM) is different than SMP >reads from the shared CPU I/O ports.
I'm simulating this with the above address check, because short of someone sending me an SNES modified to use a single >crystal oscillator used by both the SNES CPU and SMP, I can't really write more exacting tests to get the exact values here.
This is definitely one of the most extreme edge cases so far in SNES emulation.
https://archive.is/Mz9Vc
Near:
https://github.com/bsnes-emu/bsnes/commit/454b90be240ae5d06eb55665b6e23674e356552f