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bu-icsg / dana

Dynamically Allocated Neural Network Accelerator for the RISC-V Rocket Microprocessor in Chisel
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Binary Configuration uses 32-bit Pointers, ABI cleanup #45

Closed seldridge closed 6 years ago

seldridge commented 6 years ago

This refactors the binary configuration used to represent neural networks to use 32-bit pointers. This additionally refactors the codebase to remove fragility related to arbitrary choices on UInt/SInt sizes to depend on structures define in a new dana.abi package.

seldridge commented 6 years ago

Regarding larger configurations, I'm seeing a failure for this when the writes exceed the first SRAM row of the Cache (addresses in excess of 0x400). This is either some lingering fragility in bit widths or something related to the split SRAM refactor. Spot checks of the FIRRTL look okay, so I'm leaning towards the former.

Edit: It looks like this is due to SRAM banks being provided with the correct read enable signal, but the wrong write enable signal. The write enables are always routed to the first row of SRAMs.