The RTL hierarchy tab of the GOWIN FPGA Designer shows the error "ERROR EX3813 : 'CLK_14M' is not declared under prefix 'Primary'" for file rtl/src/peripheral/msx/bus.sv at line 194.
The CLK_14M signal of the BUS_IF interface was removed in previous commit "fix #7 Synchronize the operating clock with the bus clock" thus it should no longer be referenced.
Remove the unneeded assignment.
It is unclear why the assignment didn't cause other synthesis errors while building the bitstream.
The RTL hierarchy tab of the GOWIN FPGA Designer shows the error "ERROR EX3813 : 'CLK_14M' is not declared under prefix 'Primary'" for file rtl/src/peripheral/msx/bus.sv at line 194.
The CLK_14M signal of the BUS_IF interface was removed in previous commit "fix #7 Synchronize the operating clock with the bus clock" thus it should no longer be referenced.
Remove the unneeded assignment.
It is unclear why the assignment didn't cause other synthesis errors while building the bitstream.