Watchdog timer interrupt mode doesn't work

[endrjux]

Watchdog timer interrupt mode doesn't work.

When watchdog interrupt mode is enabled and system reset mode is disabled interrupt is not triggered.

It appears that when watchdog system reset is disabled (WDE bit cleared) watchdog timer is disabled completely. When WDIE bit is set it should be enabled regardless of WDE value.

Please have look at "AVR132: Using the Enhanced Watchdog Timer" figure 2-1. (http://www.atmel.com/Images/doc2551.pdf)

[bsekisser]

Working on it... See also issue #91. I am almost there but have some last few issues to iron out.

[bsekisser]

This is a link to the patch I am working on...

https://gist.github.com/bsekisser/4f89cb06ebc6ee084309#file-avr_watchdog-patch

You are welcome to look at it and test it if you could... If you see anything I might be missing or overlooking I would be grateful.. I seem to have been having an issue with the cycle timers running out after the wdt reset just now, but not familiar with the watchdog operation so I have also been trying to put together a test case to work it out.

[bsekisser]

Okay... if you haven't yet... go pull the latest diff (revision 4?) from link above and try it... I believe it should function properly... It is not ready to be pushed yet (it needs to be cleaned up and a few other details worked out, won't work with gdb yet) but should be enough to know if the watchdog function works.

[endrjux]

Ok. I'll try it and let you know.

[endrjux]

I earlier wrote that this didn't work... Patch didn't work but content of pull request #98 did.

[bsekisser]

grab and apply the most recent branch/commit I pushed early this morning... that is your best bet... if you are still having problems and think it may be interrupt related then also grab and apply the interrupt code changes by me... some of the test code I wrote and tried looked to have had some issues with the existing interrupt implementation.

[endrjux]

Yeah, just tested that. It works. :-)

[bsekisser]

It should... I (re)wrote it! ;)

[endrjux]

Please also note that in combined reset and interrupt mode (both WDIE and WDE set) WDIE bit should be cleared when interrupt is triggered. I'm not sure this is in the code. It appears to me that after timeout is triggered you check if WDIF is set to determine if this is second timeout. But WDIF should be cleared after ISR is executed.

[bsekisser]

Yes.. I remember that... Something I got to work on... Unfortunately I don't think that will be simple fix.... That I know of, interrupt enable does not normally get affected when triggered... so it goes against what simavr is set up to do, and seems to be a fairly big challenge. Will need to look at that problem for a while.

Just pushed another update.. missed a line when I cleaned it up but should be safe to test.

On Tue, 2014-10-21 at 13:35 -0700, Andrzej wrote:

Please also note that in combined reset and interrupt mode (both WDIE and WDE set) WDIE bit should be cleared when interrupt is triggered. I'm not sure this is in the code. It appears to me that after timeout is triggered you check if WDIF is set to determine if this is second timeout. But WDIF should be cleared after ISR is executed.

— Reply to this email directly or view it on GitHub.

[endrjux]

Sure, if it requires to rewrite half of simavr don't bother now. :-)

[bsekisser]

My first idea and attempt was to fudge the flags a bit when reading them... but I am looking into irq notify as servicing the interrupt clears the raised flag which also (should) call notify functions... should be able to do what is needed... trying that now.

Lets not give up just yet!

[endrjux]

Fixed in pull request #98 (commit d964ebc).