How to build the ISP algrithm into HDL code on FPGA

bxinquan / nios2_cam_isp_demo

基于verilog实现了ISP图像处理IP(Altera EP4CE6)

MIT License

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Closed Benisonpin closed 2 years ago

Benisonpin commented 2 years ago

Hi, Bxin quan: would you please share the solution,

how to build the ISP algorithm into HDL code on FPGA. 2 . Which one of FPGA is the better one, can you recommend? thanks, benison

bxinquan commented 2 years ago

这是完整的项目代码，平台是Altera EP4CE6