bytecodealliance / cranelift

Cranelift code generator
https://cranelift.readthedocs.io/
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Enumerate all legal encodings of an instruction #76

Closed stoklund closed 7 years ago

stoklund commented 7 years ago

The TargetIsa::encode() function returns the first encoding of an instruction where both ISA and instruction predicates are satisfied. We also need a way of enumerating all of the possible encodings of an instruction, probably by creating an iterator that returns encodings.

Instruction encodings can have multiple constraints that are checked at different points in the compiler pipeline:

  1. ISA predicates depend only on static settings like available CPU and instruction set features. For example, the imul.i32 instruction can only be encoded if the RISC-V "M" extension is supported by the CPU.
  2. Instruction predicates check if the immediate operands can be encoded. For example, iadd_imm.i32 can only be encoded as a RISC-V addi instruction if the immediate is a 12-bit signed integer.
  3. Register constraints. These are described by the RecipeConstraints available from EncInfo and satisfied by the register allocator.
  4. Branch range constraints. These are described by the BranchRange constraints also available from EncInfo.

Only the first two types of constraints are checked by the iterator, just like TargetISa::encode() does it. This iterator would be used by:

The tables that are generated in files like encoding-riscv.rs should already be usable for this. The implementation of TargetIsa::encode() stops at the first match. The iterator would keep going until reaching a stop code.

cc @anholt

zummenix commented 7 years ago

This can be closed. Implemented in #96