Closed candymate closed 6 months ago
If I'm not mistaken this is the same as https://github.com/bytecodealliance/wasmtime/issues/7237, right? We are writing to an unaligned address, crossing a page boundary and one of the pages triggers a fault.
I'm surprised that it works on AArch64 since that one is also supposed to be affected by this.
I would agree with @afonso360, but thanks regardless @candymate!
I'm going to close this in favor of that issue, and I'll also drop a link to https://github.com/WebAssembly/design/issues/1490 which is upstream spec discussion on this topic too.
Test Case
Steps to reproduce
Compare the following executions:
QEMU run options (riscv64) I'm currently using is the following:
Expected Results
RISC-V result should not leave side-effect when trapping. By looking at the spec, we can know that
store
instruction should check first if the memory address (offset + byte-width) is valid, then perform the memory operation.Actual Results
RISC-V leaves memory side-effects when the program traps due to invalid memory address. The PoC code posted above leaves 15 bytes of 255 at the end of the memory. (indices from 65521 to 65535)
Versions and Environment
qemu-riscv64 version 8.2.1 (v8.2.1)
Extra Info