Missing top.dcp

[ryanlkab2]

Hello,

I am trying to build your project but when I run the build_static_design.tcl, i get an error. Here is the error.

ERROR: [Common 17-69] Command failed: File 'c:/Users/xxxxxx/AppData/Roaming/Xilinx/Vivado/Static/top.dcp' does not exist

Where is this top.dcp file supposed to come from?

Thanks!

[AEW2015]

Sorry, This was not built into the script. In the Vivado project, open the synthesized design and write the checkpoint of the static hardware to that location with that name. Then run the build_static_design.tcl again. from its directory.

[ryanlkab2]

Thank you so much for replying. I didn't know if I would get a response since this project was from 2017. I am working on my Master's thesis and I am trying to do some benchmarking on PYNQ image processing. I will definitely cite you on my thesis.

I'll give this a shot and see what happens.

Thanks again, Ryan

On Mon, Nov 4, 2019, 6:41 AM Andrew E Wilson notifications@github.com wrote:

Sorry, This was not built into the script. In the Vivado project, open the synthesized design and write the checkpoint of the static hardware to that location with that name. Then run the build_static_design.tcl again. from its directory.

[image: image] https://user-images.githubusercontent.com/12721146/68118378-1d93a480-febd-11e9-8f77-3b9c48ea1d0d.png

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[AEW2015]

The next version of this will be up on GitHub soon. It includes the PYNQ video timeline with 11 partial regions supporting the mixing and copying of video streams. I will keep you updated.

[ryanlkab2]

I look forward to seeing more.

I am having a heck of a time getting this design up in Vivado. If you don't mind, would you be willing to give me a little more detail on how to get this design up and running in Vivado? Like the steps involved?

Here are the steps I took:

• I copied all of the IP files to AppData\Roaming\Xilinx\ip folder

• I loaded the PYNQ board files in C:\Xilinx\Vivado\2016.3\data\boards\board_files

• Ran the base.tcl at BYU_Senior_PYNQ_Project-master\BYU_Senior_PYNQ_Project-master\Pynq-Z1\bitstream

  • top.xdc could not be found. The constraints are missing? I see them in your BYU_Senior_PYNQ_Project-master\Pynq-Z1\vivado\base\src\constraints folder. I tried to add them after synthesis. I think my problem may be here.

• Synthesized the base design

• Opened the synthesized design and added the checkpoint top.dcp as instructed by you.

• Here is another area that I am not sure about. Do you run the build_static_design_full.tcl within the base design? I did and I get errors. Or do you close down the base design and run? (also errors) (Note I do not have a PR license so I am using your full design tcl)

• ERROR: [Place 30-415] IO Placement failed due to overutilization. This design contains 114 I/O ports while the target device: 7z020 package: clg400, contains only 75 available user I/O. The target device has 255 usable I/O pins of which 180 are already occupied by user-locked I/Os.

  • Many of these errors
  • ERROR: [Place 30-68] Instance pmodJA_data_in_IBUF[0]_inst (IBUF) is not placed ERROR: [Place 30-68] Instance pmodJA_data_in_IBUF[1]_inst (IBUF) is not placed
  • ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
  • ERROR: [Common 17-69] Command failed: Placer could not place all instances

Thanks! Ryan

On Mon, Nov 4, 2019 at 12:10 PM Andrew E Wilson notifications@github.com wrote:

The next version of this will be up on GitHub soon. It includes the PYNQ video timeline with 11 partial regions supporting the mixing and copying of video streams. I will keep you updated.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/byuccl/BYU_Senior_PYNQ_Project/issues/2?email_source=notifications&email_token=ANVORR6YFVO4XYTYSV5WB6DQSBJQ5A5CNFSM4JIOULK2YY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEDAAAFI#issuecomment-549453845, or unsubscribe https://github.com/notifications/unsubscribe-auth/ANVORRY76W6DTT6JN4RW343QSBJQ5ANCNFSM4JIOULKQ .

[ryanlkab2]

Even when I synthesize, i get this critical warning

On Mon, Nov 4, 2019 at 12:42 PM Ryan Aldridge ryanlkab2@gmail.com wrote:

I look forward to seeing more.

I am having a heck of a time getting this design up in Vivado. If you don't mind, would you be willing to give me a little more detail on how to get this design up and running in Vivado? Like the steps involved?

Here are the steps I took:

• I copied all of the IP files to AppData\Roaming\Xilinx\ip folder

• I loaded the PYNQ board files in C:\Xilinx\Vivado\2016.3\data\boards\board_files

• Ran the base.tcl at BYU_Senior_PYNQ_Project-master\BYU_Senior_PYNQ_Project-master\Pynq-Z1\bitstream

  • top.xdc could not be found. The constraints are missing? I see them in your BYU_Senior_PYNQ_Project-master\Pynq-Z1\vivado\base\src\constraints folder. I tried to add them after synthesis. I think my problem may be here.

• Synthesized the base design

• Opened the synthesized design and added the checkpoint top.dcp as instructed by you.

• Here is another area that I am not sure about. Do you run the build_static_design_full.tcl within the base design? I did and I get errors. Or do you close down the base design and run? (also errors) (Note I do not have a PR license so I am using your full design tcl)

• ERROR: [Place 30-415] IO Placement failed due to overutilization. This design contains 114 I/O ports while the target device: 7z020 package: clg400, contains only 75 available user I/O. The target device has 255 usable I/O pins of which 180 are already occupied by user-locked I/Os.

  • Many of these errors
  • ERROR: [Place 30-68] Instance pmodJA_data_in_IBUF[0]_inst (IBUF) is not placed ERROR: [Place 30-68] Instance pmodJA_data_in_IBUF[1]_inst (IBUF) is not placed
  • ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
  • ERROR: [Common 17-69] Command failed: Placer could not place all instances

Thanks! Ryan

On Mon, Nov 4, 2019 at 12:10 PM Andrew E Wilson notifications@github.com wrote:

The next version of this will be up on GitHub soon. It includes the PYNQ video timeline with 11 partial regions supporting the mixing and copying of video streams. I will keep you updated.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/byuccl/BYU_Senior_PYNQ_Project/issues/2?email_source=notifications&email_token=ANVORR6YFVO4XYTYSV5WB6DQSBJQ5A5CNFSM4JIOULK2YY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEDAAAFI#issuecomment-549453845, or unsubscribe https://github.com/notifications/unsubscribe-auth/ANVORRY76W6DTT6JN4RW343QSBJQ5ANCNFSM4JIOULKQ .

[ryanlkab2]

I must be doing something wrong in the setup

[image: image.png]

On Mon, Nov 4, 2019 at 1:34 PM Ryan Aldridge ryanlkab2@gmail.com wrote:

Even when I synthesize, i get this critical warning

On Mon, Nov 4, 2019 at 12:42 PM Ryan Aldridge ryanlkab2@gmail.com wrote:

I look forward to seeing more.

I am having a heck of a time getting this design up in Vivado. If you don't mind, would you be willing to give me a little more detail on how to get this design up and running in Vivado? Like the steps involved?

Here are the steps I took:

• I copied all of the IP files to AppData\Roaming\Xilinx\ip folder

• I loaded the PYNQ board files in C:\Xilinx\Vivado\2016.3\data\boards\board_files

• Ran the base.tcl at BYU_Senior_PYNQ_Project-master\BYU_Senior_PYNQ_Project-master\Pynq-Z1\bitstream

  • top.xdc could not be found. The constraints are missing? I see them in your BYU_Senior_PYNQ_Project-master\Pynq-Z1\vivado\base\src\constraints folder. I tried to add them after synthesis. I think my problem may be here.

• Synthesized the base design

• Opened the synthesized design and added the checkpoint top.dcp as instructed by you.

• Here is another area that I am not sure about. Do you run the build_static_design_full.tcl within the base design? I did and I get errors. Or do you close down the base design and run? (also errors) (Note I do not have a PR license so I am using your full design tcl)

• ERROR: [Place 30-415] IO Placement failed due to overutilization. This design contains 114 I/O ports while the target device: 7z020 package: clg400, contains only 75 available user I/O. The target device has 255 usable I/O pins of which 180 are already occupied by user-locked I/Os.

  • Many of these errors
  • ERROR: [Place 30-68] Instance pmodJA_data_in_IBUF[0]_inst (IBUF) is not placed ERROR: [Place 30-68] Instance pmodJA_data_in_IBUF[1]_inst (IBUF) is not placed
  • ERROR: [Place 30-99] Placer failed with error: 'IO Clock Placer failed' Please review all ERROR, CRITICAL WARNING, and WARNING messages during placement to understand the cause for failure.
  • ERROR: [Common 17-69] Command failed: Placer could not place all instances

Thanks! Ryan

On Mon, Nov 4, 2019 at 12:10 PM Andrew E Wilson notifications@github.com wrote:

The next version of this will be up on GitHub soon. It includes the PYNQ video timeline with 11 partial regions supporting the mixing and copying of video streams. I will keep you updated.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/byuccl/BYU_Senior_PYNQ_Project/issues/2?email_source=notifications&email_token=ANVORR6YFVO4XYTYSV5WB6DQSBJQ5A5CNFSM4JIOULK2YY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEDAAAFI#issuecomment-549453845, or unsubscribe https://github.com/notifications/unsubscribe-auth/ANVORRY76W6DTT6JN4RW343QSBJQ5ANCNFSM4JIOULKQ .

[AEW2015]

Is there another platform i can contact you on, we could set up a video chat maybe.

[ryanlkab2]

I don't really have anything but Skype, but I could always get something different if you have a recommendation. It's pretty cool that you would take that kind of time to help me out. It's much appreciated.

I am just new to partial reconfiguration and running designs from a .TCL. file. I'm not sure how to set everything up properly. I am obviously doing something wrong in my setup.

Do I need to copy files from your directory into my environment (other than the IP and board files)?

Thanks, Ryan

On Mon, Nov 4, 2019, 6:26 PM Andrew E Wilson notifications@github.com wrote:

Is there another platform i can contact you on, we could set up a video chat maybe.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/byuccl/BYU_Senior_PYNQ_Project/issues/2?email_source=notifications&email_token=ANVORR5UFP4GQLXNRWMX4JDQSCVQ7A5CNFSM4JIOULK2YY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEDBCFTI#issuecomment-549593805, or unsubscribe https://github.com/notifications/unsubscribe-auth/ANVORRY5VXZWKR4VMY2Z22DQSCVQ7ANCNFSM4JIOULKQ .

[ryanlkab2]

So, I deleted everything and started the build over. The first error I run into is the missing constraints file in the base.tcl build. Reading through your base.tcl, there is more code to execute after the constraints.

The issue is that the top.xdc file is in that folder. I have no idea why its not being seen. Ideas?

[image: image.png]

On Mon, Nov 4, 2019 at 8:19 PM Ryan Aldridge ryanlkab2@gmail.com wrote:

I don't really have anything but Skype, but I could always get something different if you have a recommendation. It's pretty cool that you would take that kind of time to help me out. It's much appreciated.

I am just new to partial reconfiguration and running designs from a .TCL. file. I'm not sure how to set everything up properly. I am obviously doing something wrong in my setup.

Do I need to copy files from your directory into my environment (other than the IP and board files)?

Thanks, Ryan

On Mon, Nov 4, 2019, 6:26 PM Andrew E Wilson notifications@github.com wrote:

Is there another platform i can contact you on, we could set up a video chat maybe.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/byuccl/BYU_Senior_PYNQ_Project/issues/2?email_source=notifications&email_token=ANVORR5UFP4GQLXNRWMX4JDQSCVQ7A5CNFSM4JIOULK2YY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEDBCFTI#issuecomment-549593805, or unsubscribe https://github.com/notifications/unsubscribe-auth/ANVORRY5VXZWKR4VMY2Z22DQSCVQ7ANCNFSM4JIOULKQ .

[ryanlkab2]

I was able to work through the previous issues. It was all directory issues. I was able to get the base design regenerated and the build_static_design regenerated.

Now I am onto the part_proj_gen and ran into a black box error. Any ideas?

[image: image.png]

Thanks!

On Mon, Nov 4, 2019 at 10:18 PM Ryan Aldridge ryanlkab2@gmail.com wrote:

So, I deleted everything and started the build over. The first error I run into is the missing constraints file in the base.tcl build. Reading through your base.tcl, there is more code to execute after the constraints.

The issue is that the top.xdc file is in that folder. I have no idea why its not being seen. Ideas?

[image: image.png]

On Mon, Nov 4, 2019 at 8:19 PM Ryan Aldridge ryanlkab2@gmail.com wrote:

I don't really have anything but Skype, but I could always get something different if you have a recommendation. It's pretty cool that you would take that kind of time to help me out. It's much appreciated.

I am just new to partial reconfiguration and running designs from a .TCL. file. I'm not sure how to set everything up properly. I am obviously doing something wrong in my setup.

Do I need to copy files from your directory into my environment (other than the IP and board files)?

Thanks, Ryan

On Mon, Nov 4, 2019, 6:26 PM Andrew E Wilson notifications@github.com wrote:

Is there another platform i can contact you on, we could set up a video chat maybe.

— You are receiving this because you authored the thread. Reply to this email directly, view it on GitHub https://github.com/byuccl/BYU_Senior_PYNQ_Project/issues/2?email_source=notifications&email_token=ANVORR5UFP4GQLXNRWMX4JDQSCVQ7A5CNFSM4JIOULK2YY3PNVWWK3TUL52HS4DFVREXG43VMVBW63LNMVXHJKTDN5WW2ZLOORPWSZGOEDBCFTI#issuecomment-549593805, or unsubscribe https://github.com/notifications/unsubscribe-auth/ANVORRY5VXZWKR4VMY2Z22DQSCVQ7ANCNFSM4JIOULKQ .

[ryanlkab2]

To add to my previous comment, I am running the non partial reconfig tcl files that you supplied on a different thread.
Sounds like the black box issue may be related to the non partial reconfig tcl. Like it is trying to treat it as a PR design when it is not?

[AEW2015]

What does the error message look like? And what version of Vivado are you using?

[ryanlkab2]

Here it is.

On Wed, Nov 6, 2019, 7:52 AM Andrew E Wilson notifications@github.com wrote:

What does the error message look like?

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[AEW2015]

It didn't come through, you may have to post it on the GitHub site.

[ryanlkab2]

Version 16.3

[ryanlkab2]

When base.tcl finishes and I open the synthesized design, these are the critical warnings I see. The last warning seems related to the error I get in the part_proj.tcl

[AEW2015]

It seems that the black box that was in the static design did not get saved. I may have to rerun the script on that version of Vivado. I will get back to you after I have rerun the scripts.

Here is my email andrew.e.wilson@byu.edu I am working on my thesis as well concerning this area of study and would love to chat more about your research.