Closed yonnorc42 closed 1 month ago
We can't ignore CASCADEIN pins. We need to make sure they aren't part of the design. Fasm2bels doesn't support cascading brams but they will still give some output. So when equivalence fails because CASCADE pins exist we need to know that's the reason and it's not because the tool isn't working right.
And we do need to make sure that both designs have zero/ground on the cascade pins. Also I'm not sure we can just ignore net equivalency because it's possible the ground signal connecting to them is generated by a LUT
@reillymck
We can't ignore CASCADEIN pins. We need to make sure they aren't part of the design. Fasm2bels doesn't support cascading brams but they will still give some output. So when equivalence fails because CASCADE pins exist we need to know that's the reason and it's not because the tool isn't working right.
What do you mean by "We need to make sure they aren't part of the design"?
"So when equivalence fails because CASCADE pins exist we need to know that's the reason and it's not because the tool isn't working right." So do we want the designs with the CASCADE pins to fail? Should I not worry about these designs?
Sorry. They can be part of the design but we need to make sure the value on the pin is zero or ground.
I have no idea why pylint is mad but this should be ready to merge otherwise
@jgoeders Thanks. This is ready for merge now.