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byuccl / bfasst

Tools for FPGA Assurance Flows
Apache License 2.0
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rand_soc_dumped can't run twice in a row #487

Closed dallinjdahl closed 3 months ago

dallinjdahl commented 5 months ago

If you run python scripts/run.py tests/ci/randsoc_dumped.yaml twice in a row, it will fail with a cyclic dependency. This occurs because the synth_tool picks up all the verilog files in the directory, including the implemented verilog netlist.

The relevant lines are here: https://github.com/byuccl/bfasst/blob/2e4d3f990b22457d56b503d91bd42f1c68a6de12/bfasst/tools/synth/synth_tool.py#L41-L55

We should either specify all dependencies explicitly, or we should treat dependency directories as untouchable, completely separate from the outputs. I personally think I favor the former.

reillymck commented 5 months ago

We need to bring back the design.yaml to be able to include/exclude specific verilog files. We also need to remove the part config from the design yaml parser

reillymck commented 5 months ago

The design.yaml is being processed to some degree, because jpegencode was not working and I did edit the config file here: https://github.com/byuccl/bfasst/pull/475/files#diff-2efcc07f81fa96d19d539dfcebe73b02c4b1957119511d376f43fe4c3f9eaec7 I also edited the yaml parser and it compiled again. The synth tool searching for verilog files may/may not be redundant.