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byuccl / iprec

Xilinx CoreGen module recognition project. Lead author Corey Simpson.
Apache License 2.0
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Unittest #10

Closed reillymck closed 1 year ago

reillymck commented 1 year ago

Beginning framework for unittests. Currently runs a test for compare_v.import_design(), and compare_v_refactor.import_design. Test is not comprehensive and does not currently check for accuracy, but checks that import_design produces the same result as corey's code + the bug fixes in my other PR.

reillymck commented 1 year ago

I have a committed design in test_reaources (aes128). I plan on adding a simpler design as well. I intended for the tests.py to cover all files, but we can do a separate test file for each one for sure. I wrote tests to make sure the refactor functions matched what Corey had (minus bugs). I do think I can add some functionality tests.

reillymck commented 1 year ago

I didn't intend for the previous commit to change (unless there was a bug fix) but the previous commit to be Corey's code as baseline.

dallinjdahl commented 1 year ago

Got it. I was more thinking that if we tested to make sure the code works, then it doesn't really matter if it matches Corey's. Granted, it's often hard to know if it works :)

reillymck commented 1 year ago

I agree for functionality, Corey's can just be a start to make sure we aren't doing worse. Over the next couple weeks I'll put in some functionality tests.