Documentation improvements and clarifications

[thunder-hammer]

A user of the documentation suggested the following improvements

• The documentation is too FPGA specific and it should be expanded out to include asic designer and others
• It is not clear how to specify the top level of the netlist. Not clear what it is or how to specify it.
• The terminology needs to be made more consistent. the following are not clear
  • definition of library our user said the following was not clear "This netlist element contains an ordered collection of cell or module definitions associated with a library.” In particular, the term “cell definition” or “module definition” used in the netlist definition doesn’t seem to be defined anywhere. If it is defined, we should have some cross links to make this more clear. I think it will be important to be very clear here as readers may get confused on “common” “well accepted” definitions vs. the SpydrNet definition
  • same point with definition It references a “component” but I can’t find a definition of what “Component” means.
• The figure for the api specification does not include instances other than a top instance. Additional instances should be included to show off that our tool can have more than just one instance.
• the figure for api specification is also lacking in some labeling the labels should be added to the figure for ports, cables, inner pins, outer pins, instances need to be better labled. The figure is perhaps a good start but it would be nice to have more
• a good explanation of inner and outer pins. including these in the diagram would be helpful but I think an additional textual description on that topic specifically would help clear up some confusion.
• a better figure representing all of the data types would additionally be very useful. this would need to include both hierarchy and connectivity
• additional explanations for wires cables, bundles, pins, ports, could be useful just to clarify the terminology.

[jacobdbrown4]

• [ ] The documentation is too FPGA specific and it should be expanded out to include asic designer and others

• [ ] It is not clear how to specify the top level of the netlist. Not clear what it is or how to specify it.

• [ ] The terminology needs to be made more consistent. the following are not clear definition of library our user said the following was not clear "This netlist element contains an ordered collection of cell or module definitions associated with a library.” In particular, the term “cell definition” or “module definition” used in the netlist definition doesn’t seem to be defined anywhere. If it is defined, we should have some cross links to make this more clear. I think it will be important to be very clear here as readers may get confused on “common” “well accepted” definitions vs. the SpydrNet definition. Same point with definition It references a “component” but I can’t find a definition of what “Component” means.

• [ ] The figure for the api specification does not include instances other than a top instance. Additional instances should be included to show off that our tool can have more than just one instance.

• [ ] the figure for api specification is also lacking in some labeling the labels should be added to the figure for ports, cables, inner pins, outer pins, instances need to be better labled. The figure is perhaps a good start but it would be nice to have more

• [x] a good explanation of inner and outer pins. including these in the diagram would be helpful but I think an additional textual description on that topic specifically would help clear up some confusion.

• [ ] a better figure representing all of the data types would additionally be very useful. this would need to include both hierarchy and connectivity

• [ ] additional explanations for wires cables, bundles, pins, ports, could be useful just to clarify the terminology.