byuccl / spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.
https://byuccl.github.io/spydrnet
BSD 3-Clause "New" or "Revised" License
91 stars 22 forks source link

Additional Testing needed. #126

Closed thunder-hammer closed 3 years ago

thunder-hammer commented 3 years ago

There are several tests that need to be added that relate to parsing and composing and other important portions of our code.

I think we can start to make our testing framework much more robust by adding in tests that check each bug we find as we go forward.

Some tests that would be good for verilog parsing and composing escaped names: \reset[0] =/= reset[0] \reset [0] =/= reset[0] when in a port map reset{(\reset [0], \reset [1])} [1:0]\reset == {\reset [0], \reset [1]}; make sure that the escaped signals that are referred to by single bits are combined into one signal. test all things related to the port map to assignment algorithm Assign statements: assure that assign statements are maintained properly assure that they are using the assign library and not leaving strange signals lying around test assign statements written out to edif to ensure compatibility with vivado.

Make sure that edif and verilog that is not compatible with Vivado is not compiled.

The edif parser needs to have a test that makes sure that the multi bit wire functionality works great

We should test edif properties when netlists are being composed and ensure that they are working.

Not a test but a convenience It would be nice to look at Edif composers post order code and update it to make it more like vivado (change the order as little as possible) Alternatively we could move that code over to the verilog parser.

thunder-hammer commented 3 years ago

I'm taking on this issue

when in a port map reset{(\reset [0], \reset [1])} [1:0]\reset == {\reset [0], \reset [1]}; make sure that the escaped signals that are referred to by single bits are combined into one signal.

thunder-hammer commented 3 years ago

I changed gears a little bit and am doing a ton of unit testing on the verilog parser as well as cleaning it up.

thunder-hammer commented 3 years ago

Edif multi bit nets:

when reading in, multi bit nets look like name0 or name1 and they can have a rename that looks like name[0] or name[1]

thunder-hammer commented 3 years ago

The Verilog parser is much improved here and has a lot better testing. I'm going to close this.