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byuccl / spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.
https://byuccl.github.io/spydrnet
BSD 3-Clause "New" or "Revised" License
88 stars 21 forks source link

Add a script to the build documentation #134

Closed thunder-hammer closed 11 months ago

thunder-hammer commented 3 years ago

It would be nice to write a script that leverages vivado to ensure that composed netlists are parse-able with vivado. Currently this would have to be manually run.

jacobdbrown4 commented 11 months ago

Now that our Verilog parser has improved, been tested, and supports netlists other than those from Vivado, I feel that this isn't necessary.