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byuccl / spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.
https://byuccl.github.io/spydrnet
BSD 3-Clause "New" or "Revised" License
88 stars 21 forks source link

Need to document the examples #136

Open wirthlin opened 3 years ago

wirthlin commented 3 years ago

There are a lot of files used for examples. It would be nice to create a simple table in a markdown file in the same directory that gives the name, a short description of what the example does, and then some sort of size parameter so we can get a feel for its complexity.

https://github.com/byuccl/spydrnet/tree/master/spydrnet/support_files/EDIF_netlists

thunder-hammer commented 3 years ago

Our Verilog examples are all based on the EDIF examples. I think we have a script in the repository to generate the Verilog files from the EDIF examples. We can document that script and how to use it.

I'm not sure where all of the EDIF examples came from. Some of them may be that we need to open up a synthesized design and guess somewhat what they do. Others may have come from OpenCores.

Do we have some example netlists or hdl designs that are passed around the lab or on a server? perhaps some came from those if they exist.