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byuccl / spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.
https://byuccl.github.io/spydrnet
BSD 3-Clause "New" or "Revised" License
86 stars 20 forks source link

Create a built in construct and move module/cell parameters out of the metadata #145

Open thunder-hammer opened 3 years ago

thunder-hammer commented 3 years ago

It would be nice to add the parameters into the intermediate representation direction. Currently to do a cross language conversion from EDIF to Verilog or vice versa requires the composer to look at all possible locations for parameters.

It would be nice if we added a definition.parameters and a instance.parameters call. These could in turn keep track of all possible locations for parameters ie "EDIF.parameters" or "VERILOG.Parameters" (check capitalization here)

This could clean up the metadata and make parsing and composing simpler. We should at the very least allow the usage of EDIF.parameters as a key to the metadata for backward compatibility and we should probably maintain verilog.parameters as well.

In version 2.0 it would be nice to move this out of the metadata entirely.

thunder-hammer commented 3 years ago

My first comment wouldn't be the only way to do this, it could be a new place in the meatadata for parameters. It would just be nice to untie them from a particular language.