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byuccl / spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.
https://byuccl.github.io/spydrnet
BSD 3-Clause "New" or "Revised" License
89 stars 21 forks source link

Parse .edn files #147

Closed wirthlin closed 3 years ago

wirthlin commented 3 years ago

Accept .edn files as well as .edf files for EDIf. Allow other extensions for a given format.

thunder-hammer commented 3 years ago

To add supoort for a new extension, add the desired extensions to the lists in the if checks in

_parse(filename): method in /spydrnet/parsers/__init__.py

These checks are where the parser is chosen automatically based on file extension.

This is done on the dallin_documentation branch. I'm not aware of what other extesions are common for EDIF, Let me know if there are others or create another issue if another extension surfaces.

Currently .edf .edif (.edn on dallin_documentation) are supported for edif and .v and .vh are supported for verilog. Verilog's .vo and .vqm are intentionally not parsed for now because quartus prime files contain a few constructs that would make the parser hiccup