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byuccl / spydrnet

A flexible framework for analyzing and transforming FPGA netlists. Official repository.
https://byuccl.github.io/spydrnet
BSD 3-Clause "New" or "Revised" License
91 stars 22 forks source link

Support Lattice Semiconductor netlists (Verilog based) #154

Closed wirthlin closed 1 year ago

wirthlin commented 3 years ago

We plan on supporting Lattice Semiconductor devices in 2022. We need to prepare SpyDrNet for this netlist format.

jacobdbrown4 commented 1 year ago

Lattice Radiant uses either Synplify Pro or Lattice Synthesis Engine to synthesize HDL into a netlist. The output netlist format is Verilog. We have done a lot of work getting the SpyDrNet Verilog parser/composer to work with netlists from Lattice Radiant. Everything seems to be working well for now.