Verilog parsing fails when ports implicitly mapped

[jacobdbrown4]

I have run into a problem in the Verilog parser. When a module is instantiated, the parser expects ports to be explicitly mapped like this:

my_module instance_one (.one(wire_one), .two(wire_two))

If the ports aren't explicitly mapped (so are implicitly mapped), parsing fails:

my_module instance_one (wire_one, wire_two)

This problem arose when trying to parse a verilog netlist from Lattice Radiant. I'm working on a fix.

[jacobdbrown4]

I believe I have fixed the issue. It will be included in the next release.