Verilog parser not parsing file

[emonlux]

Verilog parser is unable to fully parse my simpleCounter.v file

line 605, in parse_port_declaration AssertionError: expected port name defined in the module header to declare a port but got \FSM_sequential_cs_reg[1]_0

[jacobdbrown4]

First thing to make sure is that the verilog file is legit. Is it from Vivado or somewhere else?

[jacobdbrown4]

Also is this on the main branch or another branch?