Added pytest for multiple wire declaration

[ganeshgore]

I am trying to sync all minor changes from my version of spydrnet to keep up to date with upstream.

This PR contains a test I created to check multiple wire declarations on the single Verilog line (which was not supported in the older version) wire wire1, wire2, wire3;

I can see the current version already supports that, so I will discard my solution.

Feel free to evaluate my solution in case you find something useful. https://github.com/ganeshgore/spydrnet/blob/bf89b705c72cb48b104ad4ff24eae2b490fa5075/spydrnet/parsers/verilog/parser.py#L643-L649

[jacobdbrown4]

@ganeshgore thanks for writing this test. Can you resolve the conflicts? And then I'll accept the pull request.